Increasing integration density of various electronic devices is used as a mechanism to improve performance and/or reduce size. Integration density be enhanced by reducing a minimum device size or a stacking a plurality of dies.
Recently, a method of forming a penetration silicon via has been widely used to improve integration density. In general, a penetration silicon via is formed by forming a vertical via through a substrate and filling the via with a conductive material such as Cu.
Such a via is formed using a laser or an etching process, and the via is used to connect patterns of different layers. A ground via is formed around such a via, and the impedance of a pattern varies according to the position and shape of the ground via.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.